1. Field of the Invention
The present invention relates to a video signal decoder based on the MUSE (Multiple Sub-nyquist Sampling Encoding) system where the capacity of each frame memory employed therein can be reduced.
2. Description of the Prior Art
Referring first to FIG. 4, a description will be given on a conventional example (1) of a MUSE-format video signal decoder which employs two frame memories each having a delay time of 1-frame period. A parallel 8-bit digital video signal (digital luminance signal) (A) obtained from an input terminal 1 by three-dimensional subsampling is supplied via a noise reducer 2 to a first frame memory 3, and a digital video signal (B) outputted therefrom is supplied to a second frame memory 4.
As shown in FIG. 5, each of the first and second frame memories 3 and 4 is composed of field memories VM1 and VM2 which are cascade-connected between input and output terminals T1 and T2. Each frame memory as a whole has a capacity of 1125.times.480.times.8=4,320,000 bits (i.e., approx. 4M bits) and a delay time of 2-field periods (i.e., 1-frame period).
Subsequently, in a subtracter 5, the digital video signal (C) outputted from the frame memory 4 is subtracted from the digital video signal (A) obtained from the input terminal 1, and the resultant difference digital video signal (A - C) is supplied via a bit compressor 6 to an absolute value converter 7. (The pixel data arrangement thereof is shown in FIGS. 9(a).) Thus, an absolute-value 2-frame difference signal is obtained at an output terminal 8 of a 2-frame difference detector 2FMDK.
The bit compressor 6 is a circuit where an 8-bit difference digital video signal of -128-0-+127 levels is compressed to a 6-bit difference digital video signal of -32-0-+31 levels, as shown in FIG. 6.
The digital video signals (A), (B) and (C) represent the pixel data of the present frame, the preceding frame and the ante-preceding frame, respectively. The arrangement relationship of the pixel data on mutually corresponding scanning lines in the same odd or even field is such that, as shown in FIG. 9(a) the pixel data B is positioned between the pixel data A, and the pixel data C is positioned between the pixel data B.
The difference digital video signal (A - C) outputted from the subtracter 5 is supplied to the noise reducer 2.
The digital video signal (A) obtained from the noise reducer 2 and the digital video signal (B) from the first frame memory 3 are supplied to an interframe interpolator 9, whose output is then supplied via an output terminal 10 to an unshown still picture processor in the MUSE-format video signal decoder.
Now a 1-frame difference detector 1FMDK will be described below.
The digital video signal (A) from the noise reducer 2 is supplied to a first interpolation filter 11, while the digital video signal (B) from the first frame memory 3 is supplied to a second interpolation filter 12. In a first subtracter 13, the digital video signal (B) from the first frame memory 3 is subtracted from the interpolated digital signal (A') obtained from the first interpolation filter 11, thereby producing a first difference digital video signal (A'-B). (The pixel data arrangement thereof is shown in FIG. 9.) In a second subtracter 14, the interpolated digital video (B') obtained from the interpolation filter 12 is subtracted from the digital video signal (A) to produce a second difference digital video signal (A - B'). (The pixel data arrangement thereof is shown in FIG. 9.) The first and second difference digital video signals (A'-B) and (A - B') are supplied to a multiplexer 15, where the input signals are combined with each other. And the output therefrom is supplied via a low-pass filter 16 of a cutoff frequency 4 MHz to an absolute value converter 17 so as to be converted into an absolute value, whereby an absolute-value 1-frame difference signal is obtained from an output terminal 18.
Referring next to FIG. 7, a description will be given with regard to another conventional MUSE-format video signal decoder (2) which employs two frame memories each having a delay time of 1-field period. In FIG. 7, the same reference numerals and symbols as those used in FIG. 4 denote the same or corresponding components, and a repeated explanation thereof is omitted here. A parallel 8-bit digital video signal (A) obtained from an input terminal 1 by three-dimensional subsampling is supplied via a noise reducer 2 to a multiplexer 25. The digital video signal (A, B) outputted from the multiplexer 25 is supplied to a first frame memory 3, whose output is then supplied to a second frame memory 4. (The pixel data arrangement thereof is shown in FIG. 9.) The digital video signal (C, B) outputted from the second frame memory 4 is supplied to a demultiplexer 29, where the input signal is separated into the digital video signals (B) and (C). (The pixel data arrangement of the signal (C, B) is shown in FIG. 9.)
As shown in FIG. 8, each of the first and second frame memories 3 and 4 comprises a demultiplexer DMP connected to an input terminal T1, field memories VM1, VM2 supplied with two outputs of the demultiplexer DMP, and a multiplexer MPX supplied with outputs of the field memories and connected to an output terminal T2. Each of the frame memories has a total capacity of 1125.times.480 .times.8=4,320,000 bits (i.e., approx. 4M bits) and a delay time of 1-field period.
Now the constitution of a 2-frame difference detector 2FMDK will be described below. The digital video signal (B) obtained from the demultiplexer 29 is supplied to the multiplexer 25 and then is combined with the digital video signal (A) outputted from the noise reducer 2. In a subtracter 30, the digital video signal (C) outputted from the demultiplexer 29 is subtracted from the digital video signal (A), and a difference digital video signal (A - C) thus obtained is supplied to the noise reducer 2 while being supplied also to a bit compressor 6 which is similar to the aforementioned bit compressor 6 shown in FIG. 4, whereby bit compression is executed. The bit-compressed signal is then supplied to an absolute value converter 7, so that an absolute value 2-frame difference signal is obtained from an output terminal 8.
Next the constitution of a 1-frame difference detector 1FMDK will be described below. The output digital video signal (A, B) of the multiplexer 25 is supplied via the output terminal 10 to the still picture processor while being supplied also to a demultiplexer 26 so as to be separated into the digital video signals (A) and (B). Subsequently the digital video signal (A) and the digital video signal (-B) obtained through phase inversion by a code inverter 27 are supplied to a multiplexer 28 so as to be combined with each other. The combined digital video signal (A, -B) is then supplied via a low-pass filter 16 to an absolute value converter 17, so that an absolute-value 1-frame difference signal is obtained from an output terminal 18.
In each of the conventional examples (1) and (2), there are needed two frame memories 3 and 4 each having a capacity of 4M bits or so.